1. Field of the Invention
The present invention relates to integrated circuit structures and, more particularly, to embodiments of an integrated circuit structure that incorporates one or more asymmetric field effect transistors as a power gates (e.g., a footer and/or a header) for an electronic circuit with stacked symmetric field effect transistors.
2. Description of the Related Art
Generally, integrated circuit structures are designed with the following goals in mind: (1) decreasing device size; (2) increasing device performance (e.g., by increasing switching speed) and (3) decreasing power consumption. Device size scaling can lead to a corresponding decrease in device channel lengths and, thereby a corresponding increase in switching speed. However, it has been determined that device size scaling has its limits because short channel lengths can also lead to a number of undesirable “short-channel effects”. These short-channel effects include, but are not limited, a reduction in threshold voltage (Vt), an increase in drain leakage current, punch through (i.e., diffusion of dopants from the source and drain into the channel), and drain induced barrier lowering (DIBL). To reduce or overcome such short-channel effects without reducing switching speed, asymmetric field effect transistors have been developed. Unfortunately, there are disadvantages associated with stacking such asymmetric field effect transistors.